This invention relates to the field of semiconductor manufacture, and more particularly to a method used to reduce undesired capacitive coupling between adjacent conductive structures. An inventive structure resulting from the method is also described.
During the formation of semiconductor devices such as dynamic random access memories (DRAM), static random access memories (SRAM), logic devices, and microprocessors, several structures are commonly formed. For example, parallel metal lines such as data lines as well as other conductive interconnects and buses are formed to provide an electrical pathway, for example a pathway for data bits to and from storage capacitors on a semiconductor memory device. As a goal in semiconductor device design is to minimize device dimensions and maximize density, many of the conductive lines are formed in close proximity to adjacent lines. Contrary to this goal is the effect of capacitive coupling between adjacent lines. To reduce capacitive coupling, the spacing between lines must be sufficiently wide to ensure any electrical effects created by the coupling are minimized so that incorrect data, clock and signal timing problems, power draw due to capacitor coupling, signal noise corruption, and device lockup do not result.
A method used during the formation of a semiconductor device which allows for closer formation of device features, and the structure having increased feature density which results therefrom, would be desirable.
The present invention provides a new method that, among other advantages, reduces problems associated with the manufacture of semiconductor devices. A particular problem with current manufacturing methods includes increased device size resulting from forming sufficiently spaced (widely spaced) parallel conductive lines to reduce capacitive coupling.
In accordance with one embodiment of the invention, a group of at least three conductive lines is formed, with the lines in close proximity to each other. Two lateral lines will be functional in a semiconductor device while a center line interposed between the two lateral lines is sacrificial. A first dielectric layer is formed over and between the conductive lines. In one embodiment a void (tunnel or gap) forms between each lateral conductive line and the center line due to the lack of a complete fill of dielectric between the lines. In another embodiment, these voids do not form. In either case, after formation of the first dielectric layer the center line is exposed, for example using an opening in the first dielectric layer of the type commonly used for a contact opening. At least a portion of the exposed center line is removed using a wet or dry etch, while the first dielectric layer remains in place over the two lateral lines so they are not etched. A second dielectric layer is formed over the three conductive lines which fills the opening in the first dielectric layer but not the underlying void created by removal of the exposed center. In various embodiments, one or three air gaps remain interposed between the two lateral conductive lines. These air gaps reduce capacitive coupling in the remaining lateral lines when compared with a solid dielectric layer. Wafer processing continues according to means known in the art.
Further advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.